In recent years the performance (such as bandwidth) of parts, such as processors, included in information processing systems, such as servers and computers, have improved significantly. In order to widen the total bandwidth of an entire information processing system, it is desirable to use a high-speed transmitter-receiver circuit which transmits and receives data between parts such as processors. In order to compensate for data signal degradation which occurs in a communication channel, an equalizer is used in a receiver circuit which performs high-speed data communication.
A direct feedback decision feedback equalizer (DFE) is known as one of equalizers. This DFE adjusts a decision threshold in a comparator circuit which decides a value of an input signal by offset voltage corresponding to an amount of signal degradation that occurs due to a past value of the input signal as a result of inter-symbol interference (ISI) to compensate for the signal degradation. In order to compensate for the input signal every bit, the decision threshold in the comparator circuit is changed every time corresponding to the width of 1-bit data (unit interval (UI)).
However, a circuit, such as a current adder, having long delay time is used as an offset voltage application circuit included in a feedback loop of a direct feedback DFE. Accordingly, if a UI becomes shorter with an increase in data rate, it is difficult to make delay time of the feedback loop shorter than or equal to a UI.
On the other hand, a speculative DFE is known as a DFE in which delay time of a feedback loop is short. With a speculative DFE, offset voltage corresponding to an ISI is given in advance to an input signal whose value is to be decided by a comparator circuit and one of a plurality of signals whose values are decided by comparator circuits is selected and outputted by a selection circuit according to a decision result of a past value. By doing so, signal degradation is compensated for. Usually delay time of a selection circuit is shorter than delay time of an offset voltage application circuit used in a direct feedback DFE. As a result, delay time of a feedback loop of a speculative DFE is short compared with a direct feedback DFE.
Sam Palermo, “ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010”, Texas A&M University, (search was conducted on Jul. 28, 2015), <URL: www.ece.tamu.edu/˜spalermo/ecen689/lecture19_ee689_rx_dfe_eq.pdf>
R. Payne et al, “A 6.25-Gb/s Binary Transceiver in 0.13-um CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels,” JSSC, vol. 40, no. 12, December 2005, pp. 2646-2657
Peter Park, “A 4PAM/2PAM coaxial cable receiver analog front-end targeting 40 Gb/s in 90-nm CMOS”, A Thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto, (search was conducted on Jul. 28, 2015), <URL: tspace.library.utoronto.ca/bitstream/1807/11160/1/Park_Pet er_200806_MASc_thesis.pdf>
Optical Internetworking Forum (OIF), “Evolution of System Electrical Interfaces Towards 400G Transport”, (search was conducted on Jul. 28, 2015), <URL: www.oiforum.com/public/documents/30921b_Combined_Mkt_Focus_ECOC_Panel_OIF.pdf>
By the way, in recent years standards for data communication using four-level pulse amplitude modulation (PAM) in place of a two-level modulation transmission system, such as non return to zero (NRZ), have been created in order to realize data communication at higher data rates.
If four or more level modulation is used, the number of ISIs which may occur is large compared with the case of NRZ. As a result, the number of comparator circuits used in a speculative DFE is significantly large compared with the case of NRZ. This leads to an increase in the power consumption of comparator circuits and an increase in the power consumption of circuits which drive the comparator circuits.